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Accelerate your design processes to take advantage of the performance enhancing Chip Scale Atomic Clock CSAC technology with Chronos’ CSAC Design Services.


Fundamental research and product realisation has been on-going with regard to Chip Scale Atomic Clock (CSAC) technology at the National Institute of Standards and Technology (NIST) and Microsemi for over 10 years1,2. CSAC is arguably the biggest leap forward in oscillator stability, size, and power consumption performance in the last 35 years.  With a frequency stability comparable to today’s low cost Rubidium (Rb) atomic frequency standards, but at only 5% of the power consumption, CSAC is the ideal candidate for new tactical designs where holdover performance together with low power consumption and small form factor are critical to your product requirements.

Early adopters need to accelerate their design process to take advantage of this performance enhancing technology. With Chronos Technology’s 25 years’ experience in phase locked loop (PLL) design, oscillator integration and system testing, we can assist early adopters to accelerate CSAC implementation.


Disciplining Oscillators

High specification/quality oscillators are generally not designed into complex equipment to only ever operate in free run mode. Commonly they are disciplined by a source of better timing stability e.g. GPS and their capabilities are used to improve the medium term variation in the timing signal (wander).

This, for many applications such as portable radio or RF emitter systems, is likely to be the case for CSAC which will be designed into a PLL or have its drift corrected using a numerically controlled oscillator (NCO). Key characteristics must be analysed to ensure the PLL or NCO design is optimised. These include performance under varying environmental conditions, particularly temperature, the granularity of the oscillator control, and hold-over performance in the event of loss of the disciplining source.